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Welcome to the Memory Organization MCQs Page

Dive deep into the fascinating world of Memory Organization with our comprehensive set of Multiple-Choice Questions (MCQs). This page is dedicated to exploring the fundamental concepts and intricacies of Memory Organization, a crucial aspect of Computer Architecture. In this section, you will encounter a diverse range of MCQs that cover various aspects of Memory Organization, from the basic principles to advanced topics. Each question is thoughtfully crafted to challenge your knowledge and deepen your understanding of this critical subcategory within Computer Architecture.

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Check out the MCQs below to embark on an enriching journey through Memory Organization. Test your knowledge, expand your horizons, and solidify your grasp on this vital area of Computer Architecture.

Note: Each MCQ comes with multiple answer choices. Select the most appropriate option and test your understanding of Memory Organization. You can click on an option to test your knowledge before viewing the solution for a MCQ. Happy learning!

Memory Organization MCQs | Page 18 of 23

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Q171.
For paying an extra level of indirection for each memory access, the Virtual machine monitor maintains a

a.

Shadow page table

b.

Stack table

c.

Memory stack

d.

Queue

Discuss
Answer: (a).Shadow page table
Q172.
Storing the arrays as row by row order, is referred to as

a.

Row major order

b.

Column major order

c.

Row order

d.

Column order

Discuss
Answer: (a).Row major order
Q173.
Two processors running one is user process, other is operating system process, the latter is called

a.

Kernel process

b.

Supervisor process

c.

System process

d.

both a and b

Discuss
Answer: (d).both a and b
Q174.
The software that supports Virtual machines, is called a

a.

Virtual machine monitor

b.

Hypervisor

c.

Kernel

d.

both a and b

Discuss
Answer: (d).both a and b
Q175.
Average memory access time can be calculated as

a.

Average memory access time = Hit time + Miss rate

b.

Average memory access time = Hit time - Miss rate

c.

Average memory access time = Hit time + Miss rate _ Miss penalty

d.

Average memory access time = Miss rate

Discuss
Answer: (a).Average memory access time = Hit time + Miss rate
Q176.
The circuit's dynamic nature is:

a.

SRAM

b.

DRAM

c.

TRAM

d.

DIMM

Discuss
Answer: (b).DRAM
Q177.
An approach which does not change registers' and memory's content, and its not causing virtually memory's faults, is known as

a.

Hit penalty

b.

Semantically visible

c.

Semantically invisible

d.

Column order

Discuss
Answer: (c).Semantically invisible
Q178.
Dual inline memory modules (DIMMs) typically contains

a.

2 to 16 DRAMs

b.

1 to 15 DRAMs

c.

4 to 8 DRAMs

d.

2 to 12 DRAMs

Discuss
Answer: (d).2 to 12 DRAMs
Q179.
If the L2 cache is missed and the L3 cache is accessed. For a 4-core i7, which is having 8MB L3, the index size will be

a.

2^9

b.

2^13

c.

2^15

d.

2^17

Discuss
Answer: (b).2^13
Q180.
Blocking optimization is used to improve temporal locality, for reduce

a.

Hit miss

b.

Misses

c.

Hit rate

d.

Cache misses

Discuss
Answer: (b).Misses
Page 18 of 23

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