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Welcome to the Memory Organization MCQs Page

Dive deep into the fascinating world of Memory Organization with our comprehensive set of Multiple-Choice Questions (MCQs). This page is dedicated to exploring the fundamental concepts and intricacies of Memory Organization, a crucial aspect of Computer Architecture. In this section, you will encounter a diverse range of MCQs that cover various aspects of Memory Organization, from the basic principles to advanced topics. Each question is thoughtfully crafted to challenge your knowledge and deepen your understanding of this critical subcategory within Computer Architecture.

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Check out the MCQs below to embark on an enriching journey through Memory Organization. Test your knowledge, expand your horizons, and solidify your grasp on this vital area of Computer Architecture.

Note: Each MCQ comes with multiple answer choices. Select the most appropriate option and test your understanding of Memory Organization. You can click on an option to test your knowledge before viewing the solution for a MCQ. Happy learning!

Memory Organization MCQs | Page 14 of 23

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Q131.
In a direct-mapped cache of eight words (1)10 (00001two) and (29)10 (11101two) map to locations

a.

0ten (001two) and 5ten (101two)

b.

1ten (001two) and 4ten (101two)

c.

1ten (001two) and 5ten (101two)

d.

1ten (001two) and 6ten (101two)

Discuss
Answer: (c).1ten (001two) and 5ten (101two)
Q132.
The levels between the CPU and main memory were given a name of

a.

Hit time

b.

Miss rate

c.

Locality in time

d.

Cache

Discuss
Answer: (d).Cache
Q133.
Allowing the processor for continuing execution of instructions, that access data-cache while having cache miss, is known as

a.

Nonblocking cache

b.

Blocking cache

c.

Cache buffer

d.

None of above

Discuss
Answer: (a).Nonblocking cache
Q134.
Having 32-bit virtual-address, 4 KB pages and 4 bytes/page of table entry, the total no of page-table size would be

a.

1MB

b.

2MB

c.

3MB

d.

4MB

Discuss
Answer: (d).4MB
Q135.
A queue holding data while the data are waiting to be written in memory, is known as

a.

Read buffer

b.

Queue buffer

c.

Write buffer

d.

Data buffer

Discuss
Answer: (c).Write buffer
Q136.
Cache having 64 blocks and a block-size of 16 bytes, will have block-no for address 1200 map to

a.

75 modulo 64

b.

75 modulo 60

c.

70 modulo 64

d.

72 modulo 64

Discuss
Answer: (a).75 modulo 64
Q137.
The spatial locality, is also known as

a.

Temporal locality

b.

Locality in space

c.

Locality in time

d.

Spectral Locality

Discuss
Answer: (b).Locality in space
Q138.
In terms of the no of read accesses/program, the miss penalty in clock-cycles for a reading, and the reading miss-rate, is defined as

a.

Write-stall

b.

Queue buffer

c.

Write buffer

d.

Read-stall

Discuss
Answer: (d).Read-stall
Q139.
Having a cache block of 4words, having one-word-wide bank of DRAMs and the miss penalty 65, then no of bytes transferred/bus-clock cycle for a single miss will be

a.

0.2

b.

0.25

c.

0.75

d.

1.5

Discuss
Answer: (b).0.25
Q140.
The range of designs between direct-mapped and fully-associative cache, is called

a.

Set definitive

b.

Set associative

c.

Fully associative

d.

Block associative

Discuss
Answer: (b).Set associative
Page 14 of 23

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